Voltage regulators are often used to provide a relatively constant voltage source to other electronic circuits. A low drop-out regulator (hereinafter referred to as an “LDO regulator”) is a linear voltage regulator that is useful in applications where it is desired to maintain a regulated voltage that is relatively close to the input voltage. For example, LDO regulators are useful in battery-powered applications where the power supply voltage is exceedingly low.
A typical LDO regulator (100) is shown in FIG. 1. The LDO regulator (100) includes a PMOS transistor (P1), a first resistor (R1), a second resistor (R2), an error amplifier (Al), and a reference generator (RGEN). The PMOS transistor (P 1) has a drain that is connected to an output terminal (OUT), a gate that is connected to a control node NC, and a source that is connected to an input voltage (VIN). The first resistor (R1) is series connected between the output terminal (VREG) and a feedback node (NFB). The second resistor (R2) is series connected between node NFB and a circuit ground (GND). The error amplifier (Al) has an input connected to a reverence node (NR), a second input connected to node NFB, and an output connected to node NC. The reference generator has an output that is connected to node NR.
A load (ZL) is connected between the output terminal (OUT) and the circuit ground (GND). The LDO regulator (100) controls the gate of the PMOS transistor (P1) to ensure that regulation of the output voltage (VOUT) is maintained. The error amplifier (A1) monitors a sense voltage (VSNS) at node NFB and controls the gate of the PMOS transistor (P1) by providing a gate control signal (VGATE) at node NC. Resistors R1 and R2 form a resistor divider that produces the sense voltage (VSNS) as a percentage of the output voltage (VOUT). When VSNS and the reference signal (VREF) are substantially the same, the LDO is properly maintaining regulation of the output voltage to the load (ZL).